// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32test\dma\dmasim.cpp

// DMA framework Platform Specific Layer (PSL) for software-emulated

// DMA controller used for testing the DMA framework PIL.

// 

//

#include <drivers/dma.h>

#include <kernel/kern_priv.h>

const char KDmaPanicCat[] = "DMASIM";

const TInt KMemAlignMask = 3; // memory addresses passed to DMAC must be multiple of 4

typedef void (*TPseudoIsr)();

const TInt KChannelCount = 4;								// # of channels per controller

const TInt KDesCount = 256;									// # of descriptors allocated per controller

//////////////////////////////////////////////////////////////////////////////

// SOFTWARE DMA CONTROLLER SIMULATION

//////////////////////////////////////////////////////////////////////////////

class DmacSb

/** Single-buffer DMA controller software simulation */

	{

public:

	enum { ECsRun = 0x80000000 };

public:

	static void DoTransfer();

private:

	static void BurstTransfer();

private:

	static TInt CurrentChannel;

public:

	// pseudo registers

	static TUint8* SrcAddr[KChannelCount];

	static TUint8* DestAddr[KChannelCount];

	static TInt Count[KChannelCount];

	static TUint32 ControlStatus[KChannelCount];

	static TUint32 CompletionInt;

	static TUint32 ErrorInt;

	// hook for pseudo ISR

	static TPseudoIsr Isr;

	// transfer failure simulation

	static TInt FailCount[KChannelCount];

	};

TUint8* DmacSb::SrcAddr[KChannelCount];

TUint8* DmacSb::DestAddr[KChannelCount];

TInt DmacSb::Count[KChannelCount];

TUint32 DmacSb::ControlStatus[KChannelCount];

TUint32 DmacSb::CompletionInt;

TUint32 DmacSb::ErrorInt;

TPseudoIsr DmacSb::Isr;

TInt DmacSb::FailCount[KChannelCount];

TInt DmacSb::CurrentChannel;

void DmacSb::DoTransfer()

	{

	if (ControlStatus[CurrentChannel] & ECsRun)

		{

		if (FailCount[CurrentChannel] > 0 && --FailCount[CurrentChannel] == 0)

			{

			ControlStatus[CurrentChannel] &= ~ECsRun;

			ErrorInt |= 1 << CurrentChannel;

			Isr();

			}

		else

			{

			//__KTRACE_OPT(KDMA, Kern::Printf("DmacSb::DoTransfer channel %d", CurrentChannel));

			if (Count[CurrentChannel] == 0)

				{

				//__KTRACE_OPT(KDMA, Kern::Printf("DmacSb::DoTransfer transfer complete"));

				ControlStatus[CurrentChannel] &= ~ECsRun;

				CompletionInt |= 1 << CurrentChannel;

				Isr();

				}

			else

				BurstTransfer();

			}

		}

	CurrentChannel++;

	if (CurrentChannel >= KChannelCount)

		CurrentChannel = 0;

	}

void DmacSb::BurstTransfer()

	{

	//__KTRACE_OPT(KDMA, Kern::Printf("DmacSb::BurstTransfer"));

	TInt s = Min(Count[CurrentChannel], KBurstSize);

	memcpy(DestAddr[CurrentChannel], SrcAddr[CurrentChannel], s);

	Count[CurrentChannel] -= s;

	SrcAddr[CurrentChannel] += s;

	DestAddr[CurrentChannel] += s;

	}

//////////////////////////////////////////////////////////////////////////////

class DmacDb

/** Double-buffer DMA controller software simulation */

	{

public:

	enum { ECsRun = 0x80000000, ECsPrg = 0x40000000 };

public:

	static void Enable(TInt aIdx);

	static void DoTransfer();

private:

	static TInt CurrentChannel;

private:

	// internal pseudo-registers

	static TUint8* ActSrcAddr[KChannelCount];

	static TUint8* ActDestAddr[KChannelCount];

	static TInt ActCount[KChannelCount];

public:

	// externally accessible pseudo-registers

	static TUint32 ControlStatus[KChannelCount];

	static TUint8* PrgSrcAddr[KChannelCount];

	static TUint8* PrgDestAddr[KChannelCount];

	static TInt PrgCount[KChannelCount];

	static TUint32 CompletionInt;

	static TUint32 ErrorInt;

	// hook for pseudo ISR

	static TPseudoIsr Isr;

	// transfer failure simulation

	static TInt FailCount[KChannelCount];

	static TInt InterruptsToMiss[KChannelCount];

	};

TUint8* DmacDb::PrgSrcAddr[KChannelCount];

TUint8* DmacDb::PrgDestAddr[KChannelCount];

TInt DmacDb::PrgCount[KChannelCount];

TUint8* DmacDb::ActSrcAddr[KChannelCount];

TUint8* DmacDb::ActDestAddr[KChannelCount];

TInt DmacDb::ActCount[KChannelCount];

TUint32 DmacDb::ControlStatus[KChannelCount];

TUint32 DmacDb::CompletionInt;

TUint32 DmacDb::ErrorInt;

TPseudoIsr DmacDb::Isr;

TInt DmacDb::FailCount[KChannelCount];

TInt DmacDb::InterruptsToMiss[KChannelCount];

TInt DmacDb::CurrentChannel;

void DmacDb::Enable(TInt aIdx)

	{

	if (ControlStatus[aIdx] & ECsRun)

		ControlStatus[aIdx] |= ECsPrg;

	else

		{

		ActSrcAddr[aIdx] = PrgSrcAddr[aIdx];

		ActDestAddr[aIdx] = PrgDestAddr[aIdx];

		ActCount[aIdx] = PrgCount[aIdx];

		ControlStatus[aIdx] |= ECsRun;

		}

	}

void DmacDb::DoTransfer()

	{

	if (ControlStatus[CurrentChannel] & ECsRun)

		{

		if (FailCount[CurrentChannel] > 0 && --FailCount[CurrentChannel] == 0)

			{

			ControlStatus[CurrentChannel] &= ~ECsRun;

			ErrorInt |= 1 << CurrentChannel;

			Isr();

			}

		else

			{

			if (ActCount[CurrentChannel] == 0)

				{

				if (ControlStatus[CurrentChannel] & ECsPrg)

					{

					ActSrcAddr[CurrentChannel] = PrgSrcAddr[CurrentChannel];

					ActDestAddr[CurrentChannel] = PrgDestAddr[CurrentChannel];

					ActCount[CurrentChannel] = PrgCount[CurrentChannel];

					ControlStatus[CurrentChannel] &= ~ECsPrg;

					}

				else

					ControlStatus[CurrentChannel] &= ~ECsRun;

				if (InterruptsToMiss[CurrentChannel] > 0)

					InterruptsToMiss[CurrentChannel]--;

				else

					{

					CompletionInt |= 1 << CurrentChannel;

					Isr();

					}

				}

			else

				{

				TInt s = Min(ActCount[CurrentChannel], KBurstSize);

				memcpy(ActDestAddr[CurrentChannel], ActSrcAddr[CurrentChannel], s);

				ActCount[CurrentChannel] -= s;

				ActSrcAddr[CurrentChannel] += s;

				ActDestAddr[CurrentChannel] += s;

				}

			}

		}

	CurrentChannel++;

	if (CurrentChannel >= KChannelCount)

		CurrentChannel = 0;

	}

//////////////////////////////////////////////////////////////////////////////

class DmacSg

/** Scatter/gather DMA controller software simulation */

	{

public:

	enum { EChannelBitRun = 0x80000000 };

	enum { EDesBitInt = 1 };

	struct SDes

		{

		TUint8* iSrcAddr;

		TUint8* iDestAddr;

		TInt iCount;

		TUint iControl;

		SDes* iNext;

		};

public:

	static void DoTransfer();

	static void Enable(TInt aIdx);

private:

	static TInt CurrentChannel;

	static TBool IsDescriptorLoaded[KChannelCount];

public:

	// externally accessible pseudo-registers

	static TUint32 ChannelControl[KChannelCount];

	static TUint8* SrcAddr[KChannelCount];

	static TUint8* DestAddr[KChannelCount];

	static TInt Count[KChannelCount];

	static TUint Control[KChannelCount];

	static SDes* NextDes[KChannelCount];

	static TUint32 CompletionInt;

	static TUint32 ErrorInt;

	// hook for pseudo ISR

	static TPseudoIsr Isr;

	// transfer failure simulation

	static TInt FailCount[KChannelCount];

	static TInt InterruptsToMiss[KChannelCount];

	};

TUint32 DmacSg::ChannelControl[KChannelCount];

TUint8* DmacSg::SrcAddr[KChannelCount];

TUint8* DmacSg::DestAddr[KChannelCount];

TInt DmacSg::Count[KChannelCount];

TUint DmacSg::Control[KChannelCount];

DmacSg::SDes* DmacSg::NextDes[KChannelCount];

TUint32 DmacSg::CompletionInt;

TUint32 DmacSg::ErrorInt;

TPseudoIsr DmacSg::Isr;

TInt DmacSg::FailCount[KChannelCount];

TInt DmacSg::InterruptsToMiss[KChannelCount];

TInt DmacSg::CurrentChannel;

TBool DmacSg::IsDescriptorLoaded[KChannelCount];

void DmacSg::DoTransfer()

	{

	if (ChannelControl[CurrentChannel] & EChannelBitRun)

		{

		if (FailCount[CurrentChannel] > 0 && --FailCount[CurrentChannel] == 0)

			{

			ChannelControl[CurrentChannel] &= ~EChannelBitRun;

			ErrorInt |= 1 << CurrentChannel;

			Isr();

			}

		else

			{

			if (IsDescriptorLoaded[CurrentChannel])

				{

				if (Count[CurrentChannel] == 0)

					{

					IsDescriptorLoaded[CurrentChannel] = EFalse;

					if (Control[CurrentChannel] & EDesBitInt)

						{

						if (InterruptsToMiss[CurrentChannel] > 0)

							InterruptsToMiss[CurrentChannel]--;

						else

							{

							CompletionInt |= 1 << CurrentChannel;

							Isr();

							}

						}

					}

				else

					{

					TInt s = Min(Count[CurrentChannel], KBurstSize);

					memcpy(DestAddr[CurrentChannel], SrcAddr[CurrentChannel], s);

					Count[CurrentChannel] -= s;

					SrcAddr[CurrentChannel] += s;

					DestAddr[CurrentChannel] += s;

					}

				}

			// Need to test again as new descriptor must be loaded if

			// completion has just occured.

			if (! IsDescriptorLoaded[CurrentChannel])

				{

				if (NextDes[CurrentChannel] != NULL)

					{

					SrcAddr[CurrentChannel] = NextDes[CurrentChannel]->iSrcAddr;

					DestAddr[CurrentChannel] = NextDes[CurrentChannel]->iDestAddr;

					Count[CurrentChannel] = NextDes[CurrentChannel]->iCount;

					Control[CurrentChannel] = NextDes[CurrentChannel]->iControl;

					NextDes[CurrentChannel] = NextDes[CurrentChannel]->iNext;

					IsDescriptorLoaded[CurrentChannel] = ETrue;

					}

				else

					ChannelControl[CurrentChannel] &= ~EChannelBitRun;

				}

			}

		}

	CurrentChannel++;

	if (CurrentChannel >= KChannelCount)

		CurrentChannel = 0;

	}

void DmacSg::Enable(TInt aIdx)

	{

	SrcAddr[aIdx] = NextDes[aIdx]->iSrcAddr;

	DestAddr[aIdx] = NextDes[aIdx]->iDestAddr;

	Count[aIdx] = NextDes[aIdx]->iCount;

	Control[aIdx] = NextDes[aIdx]->iControl;

	NextDes[aIdx] = NextDes[aIdx]->iNext;

	IsDescriptorLoaded[aIdx] = ETrue;

	ChannelControl[aIdx] |= EChannelBitRun;

	}

//////////////////////////////////////////////////////////////////////////////

class DmacSim

/** 

 Harness calling the various DMA controller simulators periodically.

 */

	{

public:

	static void StartEmulation();

	static void StopEmulation();

	static TBool InISR();

	static void Synchronize();

private:

	enum { KPeriod = 1 }; // in ms

	enum { EDmaSimIdle=0u, EDmaSimStarted=1u, EDmaSimInISR=2u, EDmaSimStopping=0x80000000u };

	static void TickCB(TAny* aThis);

	static NTimer Timer;

	static volatile TInt StartStop;

	};

NTimer DmacSim::Timer;

volatile TInt DmacSim::StartStop;

void DmacSim::StartEmulation()

	{

	__DMA_ASSERTA(StartStop==EDmaSimIdle);

	new (&Timer) NTimer(&TickCB, 0);

	__e32_atomic_store_ord32(&StartStop, EDmaSimStarted);

	__DMA_ASSERTA(Timer.OneShot(KPeriod, EFalse) == KErrNone);

	}

void DmacSim::StopEmulation()

	{

	TInt orig = __e32_atomic_tas_ord32(&StartStop, (TInt)EDmaSimStarted, (TInt)EDmaSimStopping, 0);

	if (orig == EDmaSimIdle)

		return;		// wasn't running

	// loop until we succeed in cancelling the timer or the timer callback

	// notices that we are shutting down

	while (!Timer.Cancel() && __e32_atomic_load_acq32(&StartStop)!=EDmaSimIdle)

		{}

	__e32_atomic_store_ord32(&StartStop, EDmaSimIdle);

	}

void DmacSim::TickCB(TAny*)

	{

		{

		}

	TInt r = Timer.Again(KPeriod);

	if (r == KErrArgument)

		r = Timer.OneShot(KPeriod);

	__DMA_ASSERTA(r == KErrNone);

	}

TBool DmacSim::InISR()

	{

	return __e32_atomic_load_acq32(&StartStop) & EDmaSimInISR;

	}

void DmacSim::Synchronize()

	{

	while (InISR())

		{}

	}

//////////////////////////////////////////////////////////////////////////////

// PSL FOR DMA SIMULATION

//////////////////////////////////////////////////////////////////////////////

class DSimSbController : public TDmac

	{

public:

	DSimSbController();

private:

	static void Isr();

	// from TDmac

	virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr);

	virtual void StopTransfer(const TDmaChannel& aChannel);

	virtual TInt FailNext(const TDmaChannel& aChannel);

	virtual TBool IsIdle(const TDmaChannel& aChannel);

	virtual TInt MaxTransferSize(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo);

	virtual TUint MemAlignMask(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo);

public:

	static const SCreateInfo KInfo;

	TDmaSbChannel iChannels[KChannelCount];

	};

DSimSbController SbController;

const TDmac::SCreateInfo DSimSbController::KInfo =

	{

	KChannelCount,

	KDesCount,

	0,

	sizeof(SDmaPseudoDes),

	0,

	};

DSimSbController::DSimSbController()

	: TDmac(KInfo)

	{

	DmacSb::Isr = Isr;

	}

void DSimSbController::Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr)

	{

	TUint32 i = aChannel.PslId();

	const SDmaPseudoDes& des = HdrToDes(aHdr);

	DmacSb::SrcAddr[i] = (TUint8*) des.iSrc;

	DmacSb::DestAddr[i] = (TUint8*) des.iDest;

	DmacSb::Count[i] = des.iCount;

	DmacSb::ControlStatus[i] |= DmacSb::ECsRun;

	}

void DSimSbController::StopTransfer(const TDmaChannel& aChannel)

	{

	__e32_atomic_and_ord32(&DmacSb::ControlStatus[aChannel.PslId()], (TUint32)~DmacSb::ECsRun);

	DmacSim::Synchronize();

	}

TInt DSimSbController::FailNext(const TDmaChannel& aChannel)

	{

	DmacSb::FailCount[aChannel.PslId()] = 1;

	return KErrNone;

	}

TBool DSimSbController::IsIdle(const TDmaChannel& aChannel)

	{

	return (DmacSb::ControlStatus[aChannel.PslId()] & DmacSb::ECsRun) == 0;

	}

TInt DSimSbController::MaxTransferSize(TDmaChannel& /*aChannel*/, TUint /*aFlags*/, TUint32 /*aPslInfo*/)

	{

	return KMaxTransferSize;

	}

TUint DSimSbController::MemAlignMask(TDmaChannel& /*aChannel*/, TUint /*aFlags*/, TUint32 /*aPslInfo*/)

	{

	return KMemAlignMask;

	}

void DSimSbController::Isr()

	{

	for (TInt i = 0; i < KChannelCount; i++)

		{

		TUint32 mask = (1 << i);