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// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\include\memmodel\epoc\platform.h
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// Public header file for device drivers
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//
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// WARNING: This file contains some APIs which are internal and are subject
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// to change without notice. Such APIs should therefore not be used
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// outside the Kernel and Hardware Services package.
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//
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#ifndef __M32STD_H__
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#define __M32STD_H__
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#include <kernel/kernel.h>
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#include <kernel/kernboot.h>
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#ifdef __EPOC32__
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#include <e32rom.h>
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#else
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class TRomHeader;
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class TRomImageHeader;
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class TRomEntry;
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#endif
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//
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/********************************************
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* Hardware chunk abstraction
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********************************************/
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/**
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The list of memory types (aka cache attributes) in Kernel on ARMv6K, ARMv7 and later platforms.
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Types 0-3 can be used on all platforms. Types 4-7 can be used only on the platforms with memory type remapping.
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@see TMappingAttributes2
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@publishedPartner
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@released
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*/
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enum TMemoryType
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{
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EMemAttStronglyOrdered = 0, /**< Strongly Ordered memory.*/
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EMemAttDevice = 1, /**< Device memory.*/
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EMemAttNormalUncached = 2, /**< Uncached Normal memory. Writes may combine.*/
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EMemAttNormalCached = 3, /**< Fully cached (Write-Back, Read/Write Allocate, Normal memory).*/
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EMemAttKernelInternal4 = 4, /**< @internalComponent. Not to be used by device drivers.*/
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EMemAttPlatformSpecific5= 5, /**< Defined by Baseport - H/W independent.*/
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EMemAttPlatformSpecific6= 6, /**< Defined by Baseport - H/W specific - see ARM core's document for the details.*/
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EMemAttPlatformSpecific7= 7 /**< Defined by Baseport - H/W independent.*/
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};
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const TUint KMemoryTypeShift = 3; /**< @internalComponent. The number of bits in a TMemoryType value.*/
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const TUint KMemoryTypeMask = (1<<KMemoryTypeShift)-1; /**< @internalComponent. Mask value for extracting a TMemoryType value from a bitfield.*/
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/**
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Memory mapping permissions and attributes.
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@see TChunkCreateInfo
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@see Kern::ChunkCreate
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@see DSharedIoBuffer::New
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@see DPlatChunkHw::New
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@see Kern::ChunkPhysicalAddress
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@see Cache::SyncMemoryBeforeDmaWrite
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@see Cache::SyncMemoryBeforeDmaRead
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@see Cache::SyncMemoryBeforeDmaWrite
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@publishedPartner
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@released
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*/
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enum TMappingAttributes
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{
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// access permissions for read
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EMapAttrReadNoone=0x0, /**< Sets the memory as not readable in any mode */
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EMapAttrReadSup=0x1, /**< Sets the memory as readable only from Kernel (Supervisor) mode */
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EMapAttrReadUser=0x4, /**< Sets the memory as readable for user, hence it can be read in both user and supervisor mode*/
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EMapAttrReadMask=0xF, /**< Used for masking read attributes*/
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// access permissions for write
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EMapAttrWriteNoone=0x00, /**< Sets the memory as not writable in any mode */
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EMapAttrWriteSup=0x10, /**< Sets the memory as writable only from Kernel (Supervisor) mode */
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EMapAttrWriteUser=0x40, /**< Sets the memory as writable for user, hence it can be written in both user and supervisor mode*/
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EMapAttrWriteMask=0xF0, /**< Used for masking write attributes*/
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// access permissions for execute
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EMapAttrExecNoone=0x000, /**< Sets the memory as not executable in any mode */
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EMapAttrExecSup=0x100, /**< Sets the memory as executable only from Kernel (Supervisor) mode */
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EMapAttrExecUser=0x400, /**< Sets the memory as executable for user, hence it can be executed in both user and supervisor mode*/
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EMapAttrExecMask=0xF00, /**< Used for masking execute attributes*/
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// access permissions - popular combinations
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EMapAttrSupRo=0x01, /**< Supervisor has read only and user has no access permissions*/
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EMapAttrSupRw=0x11, /**< Supervisor has read/write and user has no access permissions*/
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EMapAttrSupRwx=0x111, /**< Supervisor has read/write/execute and user has no access permissions*/
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EMapAttrUserRo=0x14, /**< Supervisor has read/write and user has read only permissions*/
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EMapAttrUserRw=0x44, /**< Supervisor and user both have read/write permissions*/
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EMapAttrUserRwx=0x444, /**< Supervisor and user both have read/write/execute permissions*/
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EMapAttrAccessMask=0xFFF, /**< Used for masking access permissions attribute for popular combination */
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// Level 1 cache/buffer attributes
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EMapAttrFullyBlocking=0x0000, /**< Level 1 cache/buffer attributes sets the memory as uncached, unbuffered (may not be L2 cached)*/
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EMapAttrBufferedNC=0x1000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes do not coalesce (may not be L2 cached)*/
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EMapAttrBufferedC=0x2000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may not be L2 cached)*/
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EMapAttrL1Uncached=0x3000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may be L2 cached)*/
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EMapAttrCachedWTRA=0x4000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read allocate*/
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EMapAttrCachedWTWA=0x5000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read/write allocate*/
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EMapAttrCachedWBRA=0x6000, /**< Level 1 cache/buffer attributes sets the memory as write-back cached, read allocate*/
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EMapAttrCachedWBWA=0x7000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read/write allocate*/
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EMapAttrAltCacheWTRA=0x8000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read allocate, use alternate cache*/
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EMapAttrAltCacheWTWA=0x9000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read/write allocate, use alternate cache*/
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EMapAttrAltCacheWBRA=0xA000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read allocate, use alternate cache*/
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EMapAttrAltCacheWBWA=0xB000, /**< Level 1 cache/buffer attributes write-back cached, read/write allocate, use alternate cache*/
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EMapAttrL1CachedMax=0xF000, /**< Used to make memory maximally cached in L1 cache*/
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EMapAttrL1CacheMask=0xF000, /**< Used for masking L1 cache attributes*/
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// Level 2 cache attributes
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EMapAttrL2Uncached=0x00000, /**< Level 2 cache attributes used to set memory as uncached at level 2 */
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EMapAttrL2CachedWTRA=0x40000, /**< Level 2 cache attributes sets memory as write-through cached, read allocate*/
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EMapAttrL2CachedWTWA=0x50000, /**< Level 2 cache attributes sets memory as write-through cached, read/write allocate*/
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EMapAttrL2CachedWBRA=0x60000, /**< Level 2 cache attributes sets memory as write-back cached, read allocate*/
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EMapAttrL2CachedWBWA=0x70000, /**< Level 2 cache attributes sets memory as write-back cached, read/write allocate*/
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EMapAttrL2CachedMax=0xF0000, /**< Used to make memory maximally cached in L2 cache*/
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EMapAttrL2CacheMask=0xF0000, /**< Used for masking L2 cache attributes*/
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// Others
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EMapAttrCachedMax=0xFF000, /**< Used to set memory as maximally cached for system (fully cached in L1&L2 cache)*/
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EMapAttrShared=0x100000, /**< Used to set the memory as shared with other processors*/
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EMapAttrUseECC=0x200000, /**< Used for error correcting code*/
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};
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/**
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Container class for memory region's attributes.
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It is intended for ARM platforms with memory type and access permission remapping
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(arm11mpcore, arm1176, cortex_a8 and later), but could be used on any previous platform as well.
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The object of this type can replace TMappingAttributes bit mask whereever it is in use. For example:
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@code
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TChunkCreateInfo chunkInfo;
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...
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new (&chunkInfo.iMapAttr) TMappingAttributes2(EMemAttStronglyOrdered,EFalse,ETrue);
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r = Kern::ChunkCreate(chunkInfo, ...);
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@endcode
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@see TMemoryType
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@see TMappingAttributes
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@see TChunkCreateInfo
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@see Kern::ChunkCreate
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@see DSharedIoBuffer::New
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@see DPlatChunkHw::New
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@see Kern::ChunkPhysicalAddress
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@see Cache::SyncMemoryBeforeDmaWrite
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@see Cache::SyncMemoryBeforeDmaRead
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@see Cache::SyncMemoryBeforeDmaWrite
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@publishedPartner
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@released
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*/
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class TMappingAttributes2
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{
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public:
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/**
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Constructor.
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Memory is always readable by Kernel. Other attributes are defined by input parameters, as follows:
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@param aType Type (aka cache attributes) of the memory.
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@param aUserAccess True if memory is also accessed from user code, false if it is only accessible from kernel.
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@param aWritable True if memory is writable, false if this is read only memory.
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@param aExecutable True if memory contains code or data, false if it only contains data.
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Default argument value is false.
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@param aShared Shared attribute of the mapping:
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<0 Default value for the platform, e.g. Shareable for SMP, Unshareable for uni-processor.
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==0 Unshareable memory
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>0 Shareable memory
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To ensure future compatibility, use the value <0 except when absolutely neccessary.
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Default argument value is -1.
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@param aParity Parity error attribute of the mapping:
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<0 Default value for the platform (which is off on all platforms so far).
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==0 Parity error doesn't generate external abort.
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>0 Parity error generates external abort.
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To ensure future compatibility, use the value <0 except when absolutely neccessary.
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Default argument value is -1.
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@see TMemoryType
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*/
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IMPORT_C TMappingAttributes2(TMemoryType aType ,
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TBool aUserAccess ,
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TBool aWritable ,
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TBool aExecutable = EFalse,
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TInt aShared = -1,
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TInt aParity = -1);
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TMappingAttributes2(TUint aMapAttr);/**< @internalComponent*/
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TMemoryType Type(); /**< @internalComponent @return Type of the memory (aka cache attributes).*/
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TBool UserAccess(); /**< @internalComponent @return True if memory can be accessed from user code.*/
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TBool Writable(); /**< @internalComponent @return True if memory can be written into, false if this is reaad only memory.*/
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TBool Executable(); /**< @internalComponent @return True if memory can contain code and data, false if it can only contain data.*/
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TBool Shared(); /**< @internalComponent @return True if memory is shared, false if not.*/
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TBool Parity(); /**< @internalComponent @return True if parity error generates external abort, false if not.*/
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TBool ObjectType2();/**< @internalComponent @return True if the object is TMappingAttributes2, false if it is TMappingAttributes bitmask.*/
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private:
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static void Panic(TInt aPanic); /**< @internalComponent*/
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private:
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TUint32 iAttributes; /**< @internalComponent*/
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};
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/**
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@internalComponent
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*/
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inline TBool ComparePermissions(TInt aActual, TInt aRequired)
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{
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return ((aActual&EMapAttrReadMask)>=(aRequired&EMapAttrReadMask)) &&
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((aActual&EMapAttrWriteMask)>=(aRequired&EMapAttrWriteMask)) &&
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((aActual&EMapAttrExecMask)>=(aRequired&EMapAttrExecMask));
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}
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/** Hardware Chunk class
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Class representing a global mapping of I/O or global memory buffers
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@publishedPartner
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@released
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*/
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class DPlatChunkHw : public DObject
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{
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public:
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IMPORT_C static TInt New(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs);
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inline TLinAddr LinearAddress() {return iLinAddr;}
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inline TPhysAddr PhysicalAddress() {return iPhysAddr;}
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public:
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/** @internalComponent */
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static TInt DoNew(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs);
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public:
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TPhysAddr iPhysAddr; /**< @internalComponent */
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TLinAddr iLinAddr; /**< @internalComponent */
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TInt iSize; /**< @internalComponent */
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TUint iAttribs; /**< @internalComponent */ // mapping attributes
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};
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/********************************************
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* Exports from layer 2 or below of the kernel
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* which are not available to layer 1
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********************************************/
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/**
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Specifies the operation performed by the TRamZoneCallback function.
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@see TRamZoneCallback
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@publishedPartner
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@released
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*/
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enum TRamZoneOp
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{
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/** Informs the variant that a specified RAM zone is not currently
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being used and therefore it may be possible to save power by not refreshing
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this zone or, if the rest of the its RAM IC's zones are also empty, powering
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down the RAM IC.
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The TRamZoneCallback parameter aParam1 is the ID of the zone.
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
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that are the bit masks of the zones' power status.
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*/
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ERamZoneOp_PowerDown=0,
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/** Informs the variant that a specified RAM zone is now required for use
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and therefore it must be ready.
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The variant should ensure the zone is refreshed, if required, and that the
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RAM IC is powered and fully initialised.
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The TRamZoneCallback parameter aParam1 is the ID of the zone.
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
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that are the bit masks of the zones' power status.
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*/
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ERamZoneOp_PowerUp=1,
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/** Operation that informs the variant of the RAM zones that have been used
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during the initial stages of the boot process. Any RAM zones that are not
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in use may be powered down or not refreshed to save power.
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This will be the first operation requested of the variant and it is only
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issued once.
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The TRamZoneCallback parameter aParam1 is unused by this operation.
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints
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that are the bit masks of the zones' power status.
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*/
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ERamZoneOp_Init=2,
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};
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/**
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Call back function that is invoked by the kernel when its RAM allocator determines
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that an operation can be performed on a particular RAM zone.
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@publishedPartner
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@released
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@param aOp Type of operation to perform; a value of TRamZoneOp
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@param aParam1 A value whose use is defined by the TRamZoneOp to be performed
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@param aParam2 A value whose use is defined by the TRamZoneOp to be performed
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The data pointed to by aParam2 is const and therefore should not be modified
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@return KErrNone if successful, otherwise one of the system wide error codes
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@see TRamZoneOp
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*/
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typedef TInt (*TRamZoneCallback) (TRamZoneOp aOp, TAny* aParam1, const TAny* aParam2);
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/**
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Holds the number of each page type within a RAM zone.
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@see Epoc::GetRamZonePageCount()
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@publishedPartner
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316 |
@released
|
|
|
317 |
*/
|
|
|
318 |
struct SRamZonePageCount
|
|
|
319 |
{
|
|
|
320 |
TUint iFreePages; /**< The number of free pages in the RAM zone*/
|
|
|
321 |
TUint iUnknownPages; /**< The number of unknown pages in the RAM zone*/
|
|
|
322 |
TUint iFixedPages; /**< The number of fixed pages in the RAM zone*/
|
|
|
323 |
TUint iMovablePages; /**< The number of movable pages in the RAM zone*/
|
|
|
324 |
TUint iDiscardablePages;/**< The number of discardable pages in the RAM zone*/
|
|
|
325 |
TUint iReserved[4]; /**<@internalComponent reserved for internal use only*/
|
|
|
326 |
};
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|
|
327 |
|
|
|
328 |
/**
|
|
|
329 |
@publishedPartner
|
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|
330 |
@released
|
|
|
331 |
*/
|
|
|
332 |
class Epoc
|
|
|
333 |
{
|
|
|
334 |
public:
|
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|
335 |
/**
|
|
|
336 |
The types of RAM defragmentation operations.
|
|
|
337 |
@internalComponent
|
|
|
338 |
*/
|
|
|
339 |
enum TRamDefragOp
|
|
|
340 |
{
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|
|
341 |
ERamDefrag_DefragRam,
|
|
|
342 |
ERamDefrag_EmptyRamZone,
|
|
|
343 |
ERamDefrag_ClaimRamZone,
|
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|
344 |
};
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|
345 |
|
|
|
346 |
/**
|
|
|
347 |
The type of page to move with Epoc::MovePhysicalPage().
|
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|
348 |
@internalComponent
|
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|
349 |
*/
|
|
|
350 |
enum TRamDefragPageToMove
|
|
|
351 |
{
|
|
|
352 |
/**
|
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|
353 |
Move the physical page aOld.
|
|
|
354 |
*/
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|
355 |
ERamDefragPage_Physical,
|
|
|
356 |
/**
|
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|
357 |
Move the page table page that maps the linear address in the
|
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|
358 |
current thread at aOld.
|
|
|
359 |
*/
|
|
|
360 |
ERamDefragPage_PageTable,
|
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|
361 |
/**
|
|
|
362 |
Move the page table info page of the page table that maps the linear
|
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|
363 |
address in the current thread at aOld.
|
|
|
364 |
*/
|
|
|
365 |
ERamDefragPage_PageTableInfo,
|
|
|
366 |
};
|
|
|
367 |
|
|
|
368 |
|
|
|
369 |
IMPORT_C static void SetMonitorEntryPoint(TDfcFn aFunction); /**< @internalComponent */
|
|
|
370 |
IMPORT_C static void SetMonitorExceptionHandler(TLinAddr aHandler); /**< @internalComponent */
|
|
|
371 |
IMPORT_C static TAny* ExceptionInfo(); /**< @internalComponent */
|
|
|
372 |
IMPORT_C static const TRomHeader& RomHeader();
|
|
|
373 |
IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr);
|
|
|
374 |
IMPORT_C static TInt CopyToShadowMemory(TLinAddr aDest, TLinAddr aSrc, TUint32 aLength);
|
|
|
375 |
IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr);
|
|
|
376 |
IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr);
|
|
|
377 |
IMPORT_C static TInt AllocPhysicalRam(TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
|
|
|
378 |
IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
|
|
|
379 |
IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0);
|
|
|
380 |
IMPORT_C static TInt AllocPhysicalRam(TInt aNumPages, TPhysAddr* aPageList);
|
|
|
381 |
IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aNumPages, TPhysAddr* aPageList);
|
|
|
382 |
IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList);
|
|
|
383 |
IMPORT_C static TInt FreePhysicalRam(TPhysAddr aPhysAddr, TInt aSize);
|
|
|
384 |
IMPORT_C static TInt FreePhysicalRam(TInt aNumPages, TPhysAddr* aPageList);
|
|
|
385 |
IMPORT_C static TInt ClaimPhysicalRam(TPhysAddr aPhysAddr, TInt aSize);
|
|
|
386 |
IMPORT_C static TPhysAddr LinearToPhysical(TLinAddr aLinAddr);
|
|
|
387 |
IMPORT_C static void RomProcessInfo(TProcessCreateInfo& aInfo, const TRomImageHeader& aRomImageHeader); /**< @internalComponent */
|
|
|
388 |
#ifdef BTRACE_KERNEL_MEMORY
|
|
|
389 |
static TInt DriverAllocdPhysRam; // the number of bytes allocated by Epoc::AllocPhysicalRam and Epoc::FreePhysicalRam
|
|
|
390 |
static TInt KernelMiscPages; // the number of bytes of 'miscelaneous' kernel memory allocated
|
|
|
391 |
#endif
|
|
|
392 |
IMPORT_C static TInt MovePhysicalPage(TPhysAddr aOld, TPhysAddr& aNew, TRamDefragPageToMove aPageToMove=ERamDefragPage_Physical); /**< @internalComponent */
|
|
|
393 |
IMPORT_C static TInt SetRamZoneConfig(const SRamZone* aZones, TRamZoneCallback aCallback);
|
|
|
394 |
IMPORT_C static TInt GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData);
|
|
|
395 |
IMPORT_C static TInt ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask);
|
|
|
396 |
};
|
|
|
397 |
|
|
|
398 |
/**
|
|
|
399 |
@publishedPartner
|
|
|
400 |
@released
|
|
|
401 |
*/
|
|
|
402 |
class DebugSupport
|
|
|
403 |
{
|
|
|
404 |
public:
|
|
|
405 |
|
|
|
406 |
/** Bitmask values representing different breakpoint types. */
|
|
|
407 |
enum TType
|
|
|
408 |
{
|
|
|
409 |
EBreakpointGlobal = 1<<0, /**< Breakpoint appears in all processes */
|
|
|
410 |
EBreakpointLocal = 1<<1, /**< Breakpoint appears in the specified process only. */
|
|
|
411 |
};
|
|
|
412 |
|
|
|
413 |
IMPORT_C static TInt InitialiseCodeModifier(TUint& aCapabilities, TInt aMinBreakpoints);
|
|
|
414 |
IMPORT_C static void CloseCodeModifier();
|
|
|
415 |
IMPORT_C static TInt ModifyCode(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue, TUint aType);
|
|
|
416 |
IMPORT_C static TInt RestoreCode(DThread* aThread, TLinAddr aAddress);
|
|
|
417 |
|
|
|
418 |
/**
|
|
|
419 |
@internalTechnology
|
|
|
420 |
@prototype
|
|
|
421 |
*/
|
|
|
422 |
IMPORT_C static void TerminateProcess(DProcess* aProcess, const TInt aReason);
|
|
|
423 |
|
|
|
424 |
};
|
|
|
425 |
|
|
|
426 |
#ifdef __DEBUGGER_SUPPORT__
|
|
|
427 |
/**
|
|
|
428 |
@internalComponent
|
|
|
429 |
*/
|
|
|
430 |
class CodeModifier : public DBase
|
|
|
431 |
{
|
|
|
432 |
public:
|
|
|
433 |
|
|
|
434 |
/** Values for panic values in category 'CodeModifier'. */
|
|
|
435 |
enum TPanic
|
|
|
436 |
{
|
|
|
437 |
EPanicNotInitialised = 0,
|
|
|
438 |
EPanicInvalidSizeOrAlignment = 1,
|
|
|
439 |
};
|
|
|
440 |
|
|
|
441 |
/** Defines the type/size of the breakpoint - see TBreakpoint::iSize*/
|
|
|
442 |
enum TBrkType
|
|
|
443 |
{
|
|
|
444 |
EEmpty =0, //The slot is unused
|
|
|
445 |
EByte =1, //Jazelle breakpoint
|
|
|
446 |
EHalfword =2, //Thumb breakpoint
|
|
|
447 |
EWord =4 //ARM breakpoint
|
|
|
448 |
};
|
|
|
449 |
|
|
|
450 |
TInt static CreateAndInitialise(TInt aMinBreakpoints);
|
|
|
451 |
~CodeModifier();
|
|
|
452 |
void Close();
|
|
|
453 |
TInt Modify(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue);
|
|
|
454 |
TInt Restore(DThread* aThread, TLinAddr aAddress);
|
|
|
455 |
static void CodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess);
|
|
|
456 |
static DMutex& Mutex() {return *Kern::CodeSegLock();}
|
|
|
457 |
static void Fault(TPanic aPanic);
|
|
|
458 |
|
|
|
459 |
private:
|
|
|
460 |
|
|
|
461 |
/**Desribes a breakpoint slot in the pool*/
|
|
|
462 |
struct TBreakpoint
|
|
|
463 |
{
|
|
|
464 |
TUint iProcessId; //Id of the process associated to this breakpoint.
|
|
|
465 |
TUint iAddress; //The virtual address of the breakpoint
|
|
|
466 |
TUint32 iOldValue; //Will hold the original content of iAddress
|
|
|
467 |
TInt16 iSize; //Could be one of TBrkType. 0 means empty/unused, otherwise it indicates the size of the breakpoint in bytes.
|
|
|
468 |
TInt16 iPageIndex; //If iSize!=0 identifies corresponding shadowed page, or -1 if it is non-XIP page.
|
|
|
469 |
};
|
|
|
470 |
|
|
|
471 |
/** Desribes a page slot in the pool. Used for pages that are shadowed or need to be locked (for demand paging). */
|
|
|
472 |
struct TPageInfo
|
|
|
473 |
{
|
|
|
474 |
TLinAddr iAddress; //Base address of the page.
|
|
|
475 |
TInt32 iCounter; //The number of breakpoints associated with this page. 0 indicates empty slot.
|
|
|
476 |
TBool iWasShadowed; //True if the page had been already shadowed before the first breakpoint was applied,
|
|
|
477 |
//false otherwise. If true, it won't be un-shadowed after all breakpoints are removed.
|
|
|
478 |
#ifdef __DEMAND_PAGING__
|
|
|
479 |
/// If set, points to the deamnd paging lock object used to lock this page. Only applies to
|
|
|
480 |
/// RAM-loaded code.
|
|
|
481 |
DDemandPagingLock* iPagingLock;
|
|
|
482 |
#endif
|
|
|
483 |
};
|
|
|
484 |
private:
|
|
|
485 |
TBreakpoint* FindBreakpoint(DThread* aThread, TLinAddr aAddress, TInt aSize, TBool& aOverlap);
|
|
|
486 |
TBreakpoint* FindEmptyBrk();
|
|
|
487 |
TInt FindEmptyPageInfo();
|
|
|
488 |
TInt FindPageInfo(TLinAddr aAddress);
|
|
|
489 |
TInt IsRom(TLinAddr aAddress);
|
|
|
490 |
TInt WriteCode(TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue);
|
|
|
491 |
DProcess* Process(TUint aProcessId);
|
|
|
492 |
TInt SafeWriteCode(DProcess* aProcess, TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue);
|
|
|
493 |
void RestorePage(TInt aPageIndex);
|
|
|
494 |
void DoCodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess);
|
|
|
495 |
|
|
|
496 |
private:
|
|
|
497 |
TInt iPoolSize;
|
|
|
498 |
TBreakpoint* iBreakpoints; //Breakpoint pool with iPoolSize slots
|
|
|
499 |
TPageInfo* iPages; //The pool of the shadowed/locked pages with iPoolSize slots
|
|
|
500 |
TUint iPageSize;
|
|
|
501 |
TUint iPageMask;
|
|
|
502 |
};
|
|
|
503 |
|
|
|
504 |
GLREF_D CodeModifier* TheCodeModifier;
|
|
|
505 |
#endif //__DEBUGGER_SUPPORT__
|
|
|
506 |
|
|
|
507 |
|
|
|
508 |
/**
|
|
|
509 |
@internalComponent
|
|
|
510 |
*/
|
|
|
511 |
inline const TRomEntry &RomEntry(TLinAddr anAddr)
|
|
|
512 |
{return(*((const TRomEntry *)anAddr));}
|
|
|
513 |
|
|
|
514 |
/**
|
|
|
515 |
@internalComponent
|
|
|
516 |
*/
|
|
|
517 |
inline const TRomImageHeader& RomImageHeader(TLinAddr anAddr)
|
|
|
518 |
{return(*((const TRomImageHeader*)anAddr));}
|
|
|
519 |
|
|
|
520 |
/**
|
|
|
521 |
TRamDefragRequest is intended to be used by device drivers to request that RAM defragmentation
|
|
|
522 |
operations are performed.
|
|
|
523 |
|
|
|
524 |
All RAM defragmentation operations can be invoked synchronously or asynchronously.
|
|
|
525 |
The asynchronous RAM defragmentation operations can use either a TDfc or a NFastSemaphore
|
|
|
526 |
to signal to the caller that the operation has completed.
|
|
|
527 |
|
|
|
528 |
@see TDfc
|
|
|
529 |
@see NFastSemaphore
|
|
|
530 |
@publishedPartner
|
|
|
531 |
@released
|
|
|
532 |
*/
|
|
|
533 |
class TRamDefragRequest : protected TAsyncRequest
|
|
|
534 |
{
|
|
|
535 |
public:
|
|
|
536 |
IMPORT_C TRamDefragRequest();
|
|
|
537 |
IMPORT_C TInt DefragRam(TInt aPriority, TInt aMaxPages=0);
|
|
|
538 |
IMPORT_C TInt DefragRam(NFastSemaphore* aSem, TInt aPriority, TInt aMaxPages=0);
|
|
|
539 |
IMPORT_C TInt DefragRam(TDfc* aDfc, TInt aPriority, TInt aMaxPages=0);
|
|
|
540 |
IMPORT_C TInt EmptyRamZone(TUint aId, TInt aPriority);
|
|
|
541 |
IMPORT_C TInt EmptyRamZone(TUint aId, NFastSemaphore* aSem, TInt aPriority);
|
|
|
542 |
IMPORT_C TInt EmptyRamZone(TUint aId, TDfc* aDfc, TInt aPriority);
|
|
|
543 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TInt aPriority);
|
|
|
544 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, NFastSemaphore* aSem, TInt aPriority);
|
|
|
545 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TDfc* aDfc, TInt aPriority);
|
|
|
546 |
IMPORT_C TInt Result();
|
|
|
547 |
IMPORT_C void Cancel();
|
|
|
548 |
|
|
|
549 |
/**
|
|
|
550 |
Values that can be specified to control which thread priority
|
|
|
551 |
the RAM defragmentation operations are run with.
|
|
|
552 |
*/
|
|
|
553 |
enum TPrioritySpecial
|
|
|
554 |
{
|
|
|
555 |
/**
|
|
|
556 |
The RAM defragmentation operation will use the same thread priority as
|
|
|
557 |
that of the caller.
|
|
|
558 |
*/
|
|
|
559 |
KInheritPriority = -1,
|
|
|
560 |
};
|
|
|
561 |
|
|
|
562 |
private:
|
|
|
563 |
void SetupPriority(TInt aPriority);
|
|
|
564 |
|
|
|
565 |
private:
|
|
|
566 |
Epoc::TRamDefragOp iOp;
|
|
|
567 |
TUint iId;
|
|
|
568 |
TUint iMaxPages;
|
|
|
569 |
TInt iThreadPriority;
|
|
|
570 |
TPhysAddr* iPhysAddr;
|
|
|
571 |
TInt iSpare[6];
|
|
|
572 |
|
|
|
573 |
public:
|
|
|
574 |
friend class Defrag;
|
|
|
575 |
};
|
|
|
576 |
|
|
|
577 |
|
|
|
578 |
#endif
|
|
|
579 |
|