author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Mon, 03 May 2010 13:47:38 +0300 | |
changeset 102 | ef2a444a7410 |
parent 0 | a41df078684a |
child 257 | 3e88ff8f41d5 |
permissions | -rw-r--r-- |
0 | 1 |
// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32\include\memmodel\epoc\platform.h |
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// Public header file for device drivers |
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// |
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// WARNING: This file contains some APIs which are internal and are subject |
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// to change without notice. Such APIs should therefore not be used |
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// outside the Kernel and Hardware Services package. |
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// |
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#ifndef __M32STD_H__ |
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#define __M32STD_H__ |
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#include <kernel/kernel.h> |
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#include <kernel/kernboot.h> |
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#ifdef __EPOC32__ |
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#include <e32rom.h> |
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#else |
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class TRomHeader; |
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class TRomImageHeader; |
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class TRomEntry; |
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#endif |
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// |
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/******************************************** |
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* Hardware chunk abstraction |
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********************************************/ |
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/** |
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The list of memory types (aka cache attributes) in Kernel on ARMv6K, ARMv7 and later platforms. |
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Types 0-3 can be used on all platforms. Types 4-7 can be used only on the platforms with memory type remapping. |
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@see TMappingAttributes2 |
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@publishedPartner |
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@released |
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*/ |
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enum TMemoryType |
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{ |
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EMemAttStronglyOrdered = 0, /**< Strongly Ordered memory.*/ |
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EMemAttDevice = 1, /**< Device memory.*/ |
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EMemAttNormalUncached = 2, /**< Uncached Normal memory. Writes may combine.*/ |
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EMemAttNormalCached = 3, /**< Fully cached (Write-Back, Read/Write Allocate, Normal memory).*/ |
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EMemAttKernelInternal4 = 4, /**< @internalComponent. Not to be used by device drivers.*/ |
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EMemAttPlatformSpecific5= 5, /**< Defined by Baseport - H/W independent.*/ |
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EMemAttPlatformSpecific6= 6, /**< Defined by Baseport - H/W specific - see ARM core's document for the details.*/ |
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EMemAttPlatformSpecific7= 7 /**< Defined by Baseport - H/W independent.*/ |
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}; |
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const TUint KMemoryTypeShift = 3; /**< @internalComponent. The number of bits in a TMemoryType value.*/ |
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const TUint KMemoryTypeMask = (1<<KMemoryTypeShift)-1; /**< @internalComponent. Mask value for extracting a TMemoryType value from a bitfield.*/ |
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/** |
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Memory mapping permissions and attributes. |
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@see TChunkCreateInfo |
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@see Kern::ChunkCreate |
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@see DSharedIoBuffer::New |
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@see DPlatChunkHw::New |
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@see Kern::ChunkPhysicalAddress |
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@see Cache::SyncMemoryBeforeDmaWrite |
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@see Cache::SyncMemoryBeforeDmaRead |
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@see Cache::SyncMemoryBeforeDmaWrite |
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@publishedPartner |
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@released |
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*/ |
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enum TMappingAttributes |
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{ |
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// access permissions for read |
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EMapAttrReadNoone=0x0, /**< Sets the memory as not readable in any mode */ |
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EMapAttrReadSup=0x1, /**< Sets the memory as readable only from Kernel (Supervisor) mode */ |
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EMapAttrReadUser=0x4, /**< Sets the memory as readable for user, hence it can be read in both user and supervisor mode*/ |
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EMapAttrReadMask=0xF, /**< Used for masking read attributes*/ |
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// access permissions for write |
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EMapAttrWriteNoone=0x00, /**< Sets the memory as not writable in any mode */ |
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EMapAttrWriteSup=0x10, /**< Sets the memory as writable only from Kernel (Supervisor) mode */ |
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EMapAttrWriteUser=0x40, /**< Sets the memory as writable for user, hence it can be written in both user and supervisor mode*/ |
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EMapAttrWriteMask=0xF0, /**< Used for masking write attributes*/ |
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// access permissions for execute |
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EMapAttrExecNoone=0x000, /**< Sets the memory as not executable in any mode */ |
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EMapAttrExecSup=0x100, /**< Sets the memory as executable only from Kernel (Supervisor) mode */ |
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EMapAttrExecUser=0x400, /**< Sets the memory as executable for user, hence it can be executed in both user and supervisor mode*/ |
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EMapAttrExecMask=0xF00, /**< Used for masking execute attributes*/ |
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// access permissions - popular combinations |
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EMapAttrSupRo=0x01, /**< Supervisor has read only and user has no access permissions*/ |
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EMapAttrSupRw=0x11, /**< Supervisor has read/write and user has no access permissions*/ |
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EMapAttrSupRwx=0x111, /**< Supervisor has read/write/execute and user has no access permissions*/ |
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EMapAttrUserRo=0x14, /**< Supervisor has read/write and user has read only permissions*/ |
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EMapAttrUserRw=0x44, /**< Supervisor and user both have read/write permissions*/ |
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EMapAttrUserRwx=0x444, /**< Supervisor and user both have read/write/execute permissions*/ |
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EMapAttrAccessMask=0xFFF, /**< Used for masking access permissions attribute for popular combination */ |
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// Level 1 cache/buffer attributes |
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EMapAttrFullyBlocking=0x0000, /**< Level 1 cache/buffer attributes sets the memory as uncached, unbuffered (may not be L2 cached)*/ |
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EMapAttrBufferedNC=0x1000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes do not coalesce (may not be L2 cached)*/ |
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EMapAttrBufferedC=0x2000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may not be L2 cached)*/ |
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EMapAttrL1Uncached=0x3000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may be L2 cached)*/ |
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EMapAttrCachedWTRA=0x4000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read allocate*/ |
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EMapAttrCachedWTWA=0x5000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read/write allocate*/ |
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EMapAttrCachedWBRA=0x6000, /**< Level 1 cache/buffer attributes sets the memory as write-back cached, read allocate*/ |
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EMapAttrCachedWBWA=0x7000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read/write allocate*/ |
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EMapAttrAltCacheWTRA=0x8000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read allocate, use alternate cache*/ |
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EMapAttrAltCacheWTWA=0x9000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read/write allocate, use alternate cache*/ |
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EMapAttrAltCacheWBRA=0xA000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read allocate, use alternate cache*/ |
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EMapAttrAltCacheWBWA=0xB000, /**< Level 1 cache/buffer attributes write-back cached, read/write allocate, use alternate cache*/ |
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EMapAttrL1CachedMax=0xF000, /**< Used to make memory maximally cached in L1 cache*/ |
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EMapAttrL1CacheMask=0xF000, /**< Used for masking L1 cache attributes*/ |
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// Level 2 cache attributes |
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EMapAttrL2Uncached=0x00000, /**< Level 2 cache attributes used to set memory as uncached at level 2 */ |
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EMapAttrL2CachedWTRA=0x40000, /**< Level 2 cache attributes sets memory as write-through cached, read allocate*/ |
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EMapAttrL2CachedWTWA=0x50000, /**< Level 2 cache attributes sets memory as write-through cached, read/write allocate*/ |
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EMapAttrL2CachedWBRA=0x60000, /**< Level 2 cache attributes sets memory as write-back cached, read allocate*/ |
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EMapAttrL2CachedWBWA=0x70000, /**< Level 2 cache attributes sets memory as write-back cached, read/write allocate*/ |
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EMapAttrL2CachedMax=0xF0000, /**< Used to make memory maximally cached in L2 cache*/ |
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EMapAttrL2CacheMask=0xF0000, /**< Used for masking L2 cache attributes*/ |
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// Others |
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EMapAttrCachedMax=0xFF000, /**< Used to set memory as maximally cached for system (fully cached in L1&L2 cache)*/ |
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EMapAttrShared=0x100000, /**< Used to set the memory as shared with other processors*/ |
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EMapAttrUseECC=0x200000, /**< Used for error correcting code*/ |
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}; |
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/** |
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Container class for memory region's attributes. |
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It is intended for ARM platforms with memory type and access permission remapping |
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(arm11mpcore, arm1176, cortex_a8 and later), but could be used on any previous platform as well. |
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The object of this type can replace TMappingAttributes bit mask whereever it is in use. For example: |
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@code |
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TChunkCreateInfo chunkInfo; |
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... |
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new (&chunkInfo.iMapAttr) TMappingAttributes2(EMemAttStronglyOrdered,EFalse,ETrue); |
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r = Kern::ChunkCreate(chunkInfo, ...); |
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@endcode |
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@see TMemoryType |
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@see TMappingAttributes |
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@see TChunkCreateInfo |
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@see Kern::ChunkCreate |
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@see DSharedIoBuffer::New |
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@see DPlatChunkHw::New |
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@see Kern::ChunkPhysicalAddress |
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@see Cache::SyncMemoryBeforeDmaWrite |
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@see Cache::SyncMemoryBeforeDmaRead |
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@see Cache::SyncMemoryBeforeDmaWrite |
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@publishedPartner |
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@released |
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*/ |
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class TMappingAttributes2 |
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{ |
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public: |
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/** |
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Constructor. |
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Memory is always readable by Kernel. Other attributes are defined by input parameters, as follows: |
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@param aType Type (aka cache attributes) of the memory. |
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@param aUserAccess True if memory is also accessed from user code, false if it is only accessible from kernel. |
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@param aWritable True if memory is writable, false if this is read only memory. |
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@param aExecutable True if memory contains code or data, false if it only contains data. |
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Default argument value is false. |
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@param aShared Shared attribute of the mapping: |
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<0 Default value for the platform, e.g. Shareable for SMP, Unshareable for uni-processor. |
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==0 Unshareable memory |
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>0 Shareable memory |
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To ensure future compatibility, use the value <0 except when absolutely neccessary. |
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Default argument value is -1. |
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@param aParity Parity error attribute of the mapping: |
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<0 Default value for the platform (which is off on all platforms so far). |
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==0 Parity error doesn't generate external abort. |
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>0 Parity error generates external abort. |
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To ensure future compatibility, use the value <0 except when absolutely neccessary. |
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Default argument value is -1. |
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@see TMemoryType |
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*/ |
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IMPORT_C TMappingAttributes2(TMemoryType aType , |
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TBool aUserAccess , |
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TBool aWritable , |
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TBool aExecutable = EFalse, |
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TInt aShared = -1, |
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TInt aParity = -1); |
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TMappingAttributes2(TUint aMapAttr);/**< @internalComponent*/ |
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TMemoryType Type(); /**< @internalComponent @return Type of the memory (aka cache attributes).*/ |
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TBool UserAccess(); /**< @internalComponent @return True if memory can be accessed from user code.*/ |
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TBool Writable(); /**< @internalComponent @return True if memory can be written into, false if this is reaad only memory.*/ |
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TBool Executable(); /**< @internalComponent @return True if memory can contain code and data, false if it can only contain data.*/ |
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TBool Shared(); /**< @internalComponent @return True if memory is shared, false if not.*/ |
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TBool Parity(); /**< @internalComponent @return True if parity error generates external abort, false if not.*/ |
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TBool ObjectType2();/**< @internalComponent @return True if the object is TMappingAttributes2, false if it is TMappingAttributes bitmask.*/ |
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private: |
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static void Panic(TInt aPanic); /**< @internalComponent*/ |
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private: |
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TUint32 iAttributes; /**< @internalComponent*/ |
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}; |
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/** |
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@internalComponent |
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*/ |
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inline TBool ComparePermissions(TInt aActual, TInt aRequired) |
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{ |
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return ((aActual&EMapAttrReadMask)>=(aRequired&EMapAttrReadMask)) && |
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((aActual&EMapAttrWriteMask)>=(aRequired&EMapAttrWriteMask)) && |
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((aActual&EMapAttrExecMask)>=(aRequired&EMapAttrExecMask)); |
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} |
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/** Hardware Chunk class |
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Class representing a global mapping of I/O or global memory buffers |
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@publishedPartner |
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@released |
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*/ |
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class DPlatChunkHw : public DObject |
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{ |
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public: |
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IMPORT_C static TInt New(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs); |
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inline TLinAddr LinearAddress() {return iLinAddr;} |
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inline TPhysAddr PhysicalAddress() {return iPhysAddr;} |
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public: |
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/** @internalComponent */ |
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static TInt DoNew(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs); |
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public: |
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TPhysAddr iPhysAddr; /**< @internalComponent */ |
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TLinAddr iLinAddr; /**< @internalComponent */ |
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TInt iSize; /**< @internalComponent */ |
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TUint iAttribs; /**< @internalComponent */ // mapping attributes |
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}; |
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/******************************************** |
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* Exports from layer 2 or below of the kernel |
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* which are not available to layer 1 |
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********************************************/ |
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/** |
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Specifies the operation performed by the TRamZoneCallback function. |
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@see TRamZoneCallback |
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@publishedPartner |
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@released |
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*/ |
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enum TRamZoneOp |
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{ |
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/** Informs the variant that a specified RAM zone is not currently |
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being used and therefore it may be possible to save power by not refreshing |
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this zone or, if the rest of the its RAM IC's zones are also empty, powering |
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down the RAM IC. |
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The TRamZoneCallback parameter aParam1 is the ID of the zone. |
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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that are the bit masks of the zones' power status. |
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*/ |
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ERamZoneOp_PowerDown=0, |
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/** Informs the variant that a specified RAM zone is now required for use |
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and therefore it must be ready. |
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The variant should ensure the zone is refreshed, if required, and that the |
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RAM IC is powered and fully initialised. |
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The TRamZoneCallback parameter aParam1 is the ID of the zone. |
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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that are the bit masks of the zones' power status. |
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*/ |
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ERamZoneOp_PowerUp=1, |
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/** Operation that informs the variant of the RAM zones that have been used |
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during the initial stages of the boot process. Any RAM zones that are not |
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in use may be powered down or not refreshed to save power. |
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This will be the first operation requested of the variant and it is only |
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issued once. |
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The TRamZoneCallback parameter aParam1 is unused by this operation. |
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The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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that are the bit masks of the zones' power status. |
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*/ |
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ERamZoneOp_Init=2, |
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}; |
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/** |
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Call back function that is invoked by the kernel when its RAM allocator determines |
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that an operation can be performed on a particular RAM zone. |
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@publishedPartner |
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@released |
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@param aOp Type of operation to perform; a value of TRamZoneOp |
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@param aParam1 A value whose use is defined by the TRamZoneOp to be performed |
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@param aParam2 A value whose use is defined by the TRamZoneOp to be performed |
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The data pointed to by aParam2 is const and therefore should not be modified |
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@return KErrNone if successful, otherwise one of the system wide error codes |
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@see TRamZoneOp |
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*/ |
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typedef TInt (*TRamZoneCallback) (TRamZoneOp aOp, TAny* aParam1, const TAny* aParam2); |
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/** |
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Holds the number of each page type within a RAM zone. |
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@see Epoc::GetRamZonePageCount() |
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@publishedPartner |
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@released |
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*/ |
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struct SRamZonePageCount |
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{ |
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TUint iFreePages; /**< The number of free pages in the RAM zone*/ |
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TUint iUnknownPages; /**< The number of unknown pages in the RAM zone*/ |
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TUint iFixedPages; /**< The number of fixed pages in the RAM zone*/ |
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TUint iMovablePages; /**< The number of movable pages in the RAM zone*/ |
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TUint iDiscardablePages;/**< The number of discardable pages in the RAM zone*/ |
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TUint iReserved[4]; /**<@internalComponent reserved for internal use only*/ |
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}; |
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/** |
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@publishedPartner |
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@released |
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*/ |
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class Epoc |
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{ |
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public: |
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/** |
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The types of RAM defragmentation operations. |
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@internalComponent |
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*/ |
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enum TRamDefragOp |
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{ |
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ERamDefrag_DefragRam, |
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ERamDefrag_EmptyRamZone, |
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ERamDefrag_ClaimRamZone, |
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}; |
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/** |
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The type of page to move with Epoc::MovePhysicalPage(). |
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@internalComponent |
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*/ |
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enum TRamDefragPageToMove |
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{ |
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/** |
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Move the physical page aOld. |
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*/ |
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ERamDefragPage_Physical, |
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/** |
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Move the page table page that maps the linear address in the |
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current thread at aOld. |
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*/ |
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ERamDefragPage_PageTable, |
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/** |
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Move the page table info page of the page table that maps the linear |
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address in the current thread at aOld. |
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*/ |
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ERamDefragPage_PageTableInfo, |
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}; |
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IMPORT_C static void SetMonitorEntryPoint(TDfcFn aFunction); /**< @internalComponent */ |
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IMPORT_C static void SetMonitorExceptionHandler(TLinAddr aHandler); /**< @internalComponent */ |
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IMPORT_C static TAny* ExceptionInfo(); /**< @internalComponent */ |
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IMPORT_C static const TRomHeader& RomHeader(); |
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IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr); |
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IMPORT_C static TInt CopyToShadowMemory(TLinAddr aDest, TLinAddr aSrc, TUint32 aLength); |
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IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr); |
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IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr); |
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IMPORT_C static TInt AllocPhysicalRam(TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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IMPORT_C static TInt AllocPhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aNumPages, TPhysAddr* aPageList); |
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IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList); |
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IMPORT_C static TInt FreePhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
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IMPORT_C static TInt FreePhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
385 |
IMPORT_C static TInt FreeRamZone(TUint aZoneId); |
0 | 386 |
IMPORT_C static TInt ClaimPhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
387 |
IMPORT_C static TPhysAddr LinearToPhysical(TLinAddr aLinAddr); |
|
388 |
IMPORT_C static void RomProcessInfo(TProcessCreateInfo& aInfo, const TRomImageHeader& aRomImageHeader); /**< @internalComponent */ |
|
389 |
#ifdef BTRACE_KERNEL_MEMORY |
|
390 |
static TInt DriverAllocdPhysRam; // the number of bytes allocated by Epoc::AllocPhysicalRam and Epoc::FreePhysicalRam |
|
391 |
static TInt KernelMiscPages; // the number of bytes of 'miscelaneous' kernel memory allocated |
|
392 |
#endif |
|
393 |
IMPORT_C static TInt MovePhysicalPage(TPhysAddr aOld, TPhysAddr& aNew, TRamDefragPageToMove aPageToMove=ERamDefragPage_Physical); /**< @internalComponent */ |
|
394 |
IMPORT_C static TInt SetRamZoneConfig(const SRamZone* aZones, TRamZoneCallback aCallback); |
|
395 |
IMPORT_C static TInt GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData); |
|
396 |
IMPORT_C static TInt ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask); |
|
397 |
}; |
|
398 |
||
399 |
/** |
|
400 |
@publishedPartner |
|
401 |
@released |
|
402 |
*/ |
|
403 |
class DebugSupport |
|
404 |
{ |
|
405 |
public: |
|
406 |
||
407 |
/** Bitmask values representing different breakpoint types. */ |
|
408 |
enum TType |
|
409 |
{ |
|
410 |
EBreakpointGlobal = 1<<0, /**< Breakpoint appears in all processes */ |
|
411 |
EBreakpointLocal = 1<<1, /**< Breakpoint appears in the specified process only. */ |
|
412 |
}; |
|
413 |
||
414 |
IMPORT_C static TInt InitialiseCodeModifier(TUint& aCapabilities, TInt aMinBreakpoints); |
|
415 |
IMPORT_C static void CloseCodeModifier(); |
|
416 |
IMPORT_C static TInt ModifyCode(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue, TUint aType); |
|
417 |
IMPORT_C static TInt RestoreCode(DThread* aThread, TLinAddr aAddress); |
|
418 |
||
419 |
/** |
|
420 |
@internalTechnology |
|
421 |
@prototype |
|
422 |
*/ |
|
423 |
IMPORT_C static void TerminateProcess(DProcess* aProcess, const TInt aReason); |
|
424 |
||
425 |
}; |
|
426 |
||
427 |
#ifdef __DEBUGGER_SUPPORT__ |
|
428 |
/** |
|
429 |
@internalComponent |
|
430 |
*/ |
|
431 |
class CodeModifier : public DBase |
|
432 |
{ |
|
433 |
public: |
|
434 |
||
435 |
/** Values for panic values in category 'CodeModifier'. */ |
|
436 |
enum TPanic |
|
437 |
{ |
|
438 |
EPanicNotInitialised = 0, |
|
439 |
EPanicInvalidSizeOrAlignment = 1, |
|
440 |
}; |
|
441 |
||
442 |
/** Defines the type/size of the breakpoint - see TBreakpoint::iSize*/ |
|
443 |
enum TBrkType |
|
444 |
{ |
|
445 |
EEmpty =0, //The slot is unused |
|
446 |
EByte =1, //Jazelle breakpoint |
|
447 |
EHalfword =2, //Thumb breakpoint |
|
448 |
EWord =4 //ARM breakpoint |
|
449 |
}; |
|
450 |
||
451 |
TInt static CreateAndInitialise(TInt aMinBreakpoints); |
|
452 |
~CodeModifier(); |
|
453 |
void Close(); |
|
454 |
TInt Modify(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue); |
|
455 |
TInt Restore(DThread* aThread, TLinAddr aAddress); |
|
456 |
static void CodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess); |
|
457 |
static DMutex& Mutex() {return *Kern::CodeSegLock();} |
|
458 |
static void Fault(TPanic aPanic); |
|
459 |
||
460 |
private: |
|
461 |
||
462 |
/**Desribes a breakpoint slot in the pool*/ |
|
463 |
struct TBreakpoint |
|
464 |
{ |
|
465 |
TUint iProcessId; //Id of the process associated to this breakpoint. |
|
466 |
TUint iAddress; //The virtual address of the breakpoint |
|
467 |
TUint32 iOldValue; //Will hold the original content of iAddress |
|
468 |
TInt16 iSize; //Could be one of TBrkType. 0 means empty/unused, otherwise it indicates the size of the breakpoint in bytes. |
|
469 |
TInt16 iPageIndex; //If iSize!=0 identifies corresponding shadowed page, or -1 if it is non-XIP page. |
|
470 |
}; |
|
471 |
||
472 |
/** Desribes a page slot in the pool. Used for pages that are shadowed or need to be locked (for demand paging). */ |
|
473 |
struct TPageInfo |
|
474 |
{ |
|
475 |
TLinAddr iAddress; //Base address of the page. |
|
476 |
TInt32 iCounter; //The number of breakpoints associated with this page. 0 indicates empty slot. |
|
477 |
TBool iWasShadowed; //True if the page had been already shadowed before the first breakpoint was applied, |
|
478 |
//false otherwise. If true, it won't be un-shadowed after all breakpoints are removed. |
|
479 |
#ifdef __DEMAND_PAGING__ |
|
480 |
/// If set, points to the deamnd paging lock object used to lock this page. Only applies to |
|
481 |
/// RAM-loaded code. |
|
482 |
DDemandPagingLock* iPagingLock; |
|
483 |
#endif |
|
484 |
}; |
|
485 |
private: |
|
486 |
TBreakpoint* FindBreakpoint(DThread* aThread, TLinAddr aAddress, TInt aSize, TBool& aOverlap); |
|
487 |
TBreakpoint* FindEmptyBrk(); |
|
488 |
TInt FindEmptyPageInfo(); |
|
489 |
TInt FindPageInfo(TLinAddr aAddress); |
|
490 |
TInt IsRom(TLinAddr aAddress); |
|
491 |
TInt WriteCode(TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue); |
|
492 |
DProcess* Process(TUint aProcessId); |
|
493 |
TInt SafeWriteCode(DProcess* aProcess, TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue); |
|
494 |
void RestorePage(TInt aPageIndex); |
|
495 |
void DoCodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess); |
|
496 |
||
497 |
private: |
|
498 |
TInt iPoolSize; |
|
499 |
TBreakpoint* iBreakpoints; //Breakpoint pool with iPoolSize slots |
|
500 |
TPageInfo* iPages; //The pool of the shadowed/locked pages with iPoolSize slots |
|
501 |
TUint iPageSize; |
|
502 |
TUint iPageMask; |
|
503 |
}; |
|
504 |
||
505 |
GLREF_D CodeModifier* TheCodeModifier; |
|
506 |
#endif //__DEBUGGER_SUPPORT__ |
|
507 |
||
508 |
||
509 |
/** |
|
510 |
@internalComponent |
|
511 |
*/ |
|
512 |
inline const TRomEntry &RomEntry(TLinAddr anAddr) |
|
513 |
{return(*((const TRomEntry *)anAddr));} |
|
514 |
||
515 |
/** |
|
516 |
@internalComponent |
|
517 |
*/ |
|
518 |
inline const TRomImageHeader& RomImageHeader(TLinAddr anAddr) |
|
519 |
{return(*((const TRomImageHeader*)anAddr));} |
|
520 |
||
521 |
/** |
|
522 |
TRamDefragRequest is intended to be used by device drivers to request that RAM defragmentation |
|
523 |
operations are performed. |
|
524 |
||
525 |
All RAM defragmentation operations can be invoked synchronously or asynchronously. |
|
526 |
The asynchronous RAM defragmentation operations can use either a TDfc or a NFastSemaphore |
|
527 |
to signal to the caller that the operation has completed. |
|
528 |
||
529 |
@see TDfc |
|
530 |
@see NFastSemaphore |
|
531 |
@publishedPartner |
|
532 |
@released |
|
533 |
*/ |
|
534 |
class TRamDefragRequest : protected TAsyncRequest |
|
535 |
{ |
|
536 |
public: |
|
537 |
IMPORT_C TRamDefragRequest(); |
|
538 |
IMPORT_C TInt DefragRam(TInt aPriority, TInt aMaxPages=0); |
|
539 |
IMPORT_C TInt DefragRam(NFastSemaphore* aSem, TInt aPriority, TInt aMaxPages=0); |
|
540 |
IMPORT_C TInt DefragRam(TDfc* aDfc, TInt aPriority, TInt aMaxPages=0); |
|
541 |
IMPORT_C TInt EmptyRamZone(TUint aId, TInt aPriority); |
|
542 |
IMPORT_C TInt EmptyRamZone(TUint aId, NFastSemaphore* aSem, TInt aPriority); |
|
543 |
IMPORT_C TInt EmptyRamZone(TUint aId, TDfc* aDfc, TInt aPriority); |
|
544 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TInt aPriority); |
|
545 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, NFastSemaphore* aSem, TInt aPriority); |
|
546 |
IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TDfc* aDfc, TInt aPriority); |
|
547 |
IMPORT_C TInt Result(); |
|
548 |
IMPORT_C void Cancel(); |
|
549 |
||
550 |
/** |
|
551 |
Values that can be specified to control which thread priority |
|
552 |
the RAM defragmentation operations are run with. |
|
553 |
*/ |
|
554 |
enum TPrioritySpecial |
|
555 |
{ |
|
556 |
/** |
|
557 |
The RAM defragmentation operation will use the same thread priority as |
|
558 |
that of the caller. |
|
559 |
*/ |
|
560 |
KInheritPriority = -1, |
|
561 |
}; |
|
562 |
||
563 |
private: |
|
564 |
void SetupPriority(TInt aPriority); |
|
565 |
||
566 |
private: |
|
567 |
Epoc::TRamDefragOp iOp; |
|
568 |
TUint iId; |
|
569 |
TUint iMaxPages; |
|
570 |
TInt iThreadPriority; |
|
571 |
TPhysAddr* iPhysAddr; |
|
572 |
TInt iSpare[6]; |
|
573 |
||
574 |
public: |
|
575 |
friend class Defrag; |
|
576 |
}; |
|
577 |
||
578 |
||
579 |
#endif |
|
580 |