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33 to a single shared main memory system and run a single OS instance. </p><p>The |
33 to a single shared main memory system and run a single OS instance. </p><p>The |
34 diagram below shows how this would apply on the Symbian platform with four |
34 diagram below shows how this would apply on the Symbian platform with four |
35 CPU cores. <fig id="GUID-FBBCE840-E295-4287-BA10-DF37292D432B"> |
35 CPU cores. <fig id="GUID-FBBCE840-E295-4287-BA10-DF37292D432B"> |
36 <title>The Simplified Architecture of an SMP Platform Executing on the Symbian |
36 <title>The Simplified Architecture of an SMP Platform Executing on the Symbian |
37 Platform. </title> |
37 Platform. </title> |
38 <image href="GUID-85A84BAA-4FA2-4A26-A8B1-57018D8838C3_d0e16677_href.jpg" placement="inline"/> |
38 <image href="GUID-85A84BAA-4FA2-4A26-A8B1-57018D8838C3_d0e16767_href.jpg" placement="inline"/> |
39 </fig></p><p>The figure shows a simplified block diagram of an SMP system, |
39 </fig></p><p>The figure shows a simplified block diagram of an SMP system, |
40 where 4 CPUs are connected through their own cache to shared RAM and peripherals. |
40 where 4 CPUs are connected through their own cache to shared RAM and peripherals. |
41 The Cache Coherency Control block is responsible for ensuring that each CPU |
41 The Cache Coherency Control block is responsible for ensuring that each CPU |
42 cache is consistent with those of the other CPUs. A single instance of OS |
42 cache is consistent with those of the other CPUs. A single instance of OS |
43 spans the CPUs, the scheduler decides which thread to execute next and upon |
43 spans the CPUs, the scheduler decides which thread to execute next and upon |