--- a/Symbian3/PDK/Source/GUID-387E98B0-568D-4DBB-9A9E-616E41E96B58.dita	Fri Jul 02 12:51:36 2010 +0100
+++ b/Symbian3/PDK/Source/GUID-387E98B0-568D-4DBB-9A9E-616E41E96B58.dita	Fri Jul 16 17:23:46 2010 +0100
@@ -35,7 +35,7 @@
 CPU cores. <fig id="GUID-FBBCE840-E295-4287-BA10-DF37292D432B">
 <title>The Simplified Architecture of an SMP Platform Executing on the Symbian
 Platform.  </title>
-<image href="GUID-85A84BAA-4FA2-4A26-A8B1-57018D8838C3_d0e16677_href.jpg" placement="inline"/>
+<image href="GUID-85A84BAA-4FA2-4A26-A8B1-57018D8838C3_d0e16767_href.jpg" placement="inline"/>
 </fig></p><p>The figure shows a simplified block diagram of an SMP system,
 where 4 CPUs are connected through their own cache to shared RAM and peripherals.
 The Cache Coherency Control block is responsible for ensuring that each CPU