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<concept id="GUID-387E98B0-568D-4DBB-9A9E-616E41E96B58" xml:lang="en"><title>SMP

Overview</title><shortdesc>This document introduces Symmetric Multiprocessing (SMP) on the

Symbian platform.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>

<section id="GUID-105AFE3B-F000-4548-B57E-4A5EAEBA2645"><title>Purpose</title> 

     <p>An SMP operating system enables any CPU to work on any task, enabling

multiple threads (processes or multiple threads within a process, and therefore

applications) to run in parallel. </p><p>A system with 2 CPUs, for example,

can allow 2 threads to run concurrently; one on each processor. This provides

better responsiveness and asynchronicity compared to a system with a single

CPU.</p><p>An SMP system can deliver a similar level of CPU performance as

a larger and faster uni-processor CPU, while using less power. SMP also provides

additional power management flexibility, running a single CPU when the system

is under utilised then switching on extra CPUs to give scalable performance

on demand for media rich applications. The ARM SMP architecture allows power

control with voltage / frequency scaling and the ability to switch individual

cores on and off.</p><p>However, the benefits of SMP come at the cost of OS

and application complexity (the requirement of extra locks and the multithreading

of code) and the associated debugging challenges of parallel processing.</p> 

   </section>

<section id="GUID-38C8CACC-0CCD-460B-9713-B33FF79FE75B"><title>Description</title><p>SMP

is a microprocessor architecture where two or more identical CPUs are connected

to a single shared main memory system and run a single OS instance. </p><p>The

diagram below shows how this would apply on the Symbian platform with four

CPU cores. <fig id="GUID-FBBCE840-E295-4287-BA10-DF37292D432B">

<title>The Simplified Architecture of an SMP Platform Executing on the Symbian

Platform.  </title>

</fig></p><p>The figure shows a simplified block diagram of an SMP system,

where 4 CPUs are connected through their own cache to shared RAM and peripherals.

The Cache Coherency Control block is responsible for ensuring that each CPU

cache is consistent with those of the other CPUs. A single instance of OS

spans the CPUs, the scheduler decides which thread to execute next and upon

which CPU it should execute. </p></section>

<section id="GUID-1672A908-7BE6-4261-997B-2495C598A6E0"><title>SMP features</title><p>The

features of the SMP platform are: <ul>

<li><p><b>Better responsiveness</b></p><p>One or more CPU cores can be dedicated

to IO related work. </p></li>

<li><p><b>High performance on demand</b></p><p>Work can be moved onto CPUs

when required. </p></li>

<li><p><b>Flexible power management</b></p><p> CPU cores can be switched on

or off, or voltage/frequency scaled, according to the current processing requirements

of the system.</p><p>This can lead to improved battery life because the system

only uses as much processing power as required at any given time.</p></li>

<li><p><b>Scalable architecture</b></p><p>SMP can work over two or more CPU

cores. </p></li>

</ul></p></section>

<section id="GUID-D4A04CA3-2E37-4DE1-BF98-C08365F8DFB0"><title>SMP limitations</title><p>The

disadvantages of using SMP are: </p><ul>

<li><p><b>The original emulator for the Symbian platform will not emulate

an SMP environment</b></p><p>The emulator is being replaced by a new emulation

environment that is capable of simulating the multiprocessor environment.</p></li>

<li><p><b>Software changes are required</b></p><p>Assumptions that can be

made in a single core environment, are not necessarily true on a multi-core

system. The SMP-safe documentation you are reading now will provide you with

guidance on a number of issues sure to come up while migrating your software

to work in an SMP environment.</p></li>

<li><p><b>Debugging Challenges</b></p><p>Debugging on a multi-processor system

is extremely difficult. The standard tooling solutions, such as the Lauterbach

debugger and BTrace2 (also known as the modified BTrace) have been revised

to handle the special requirements of an SMP system.</p></li>

<li><p><b>Access to memory is serialized</b></p><p>All the CPU cores use the

same memory, memory access must occur serially. This can cause a performance

lag. </p></li>

</ul></section>

</conbody><related-links>

<link href="GUID-242D9F27-401B-4230-B3A6-11E2D9D3DE17.dita"><linktext>Threading

Model</linktext></link>

<link href="GUID-16AED228-539F-4BF7-A7FD-9A01FF1A9A84.dita"><linktext>Locking</linktext>

</link>

<link href="GUID-9D93F895-B975-4F2D-A2A3-817033EA5C12.dita"><linktext>Data Integrity

and Memory Barriers</linktext></link>

<link href="GUID-821C254A-40C6-45F9-B2F9-2CF28CAEB8CC.dita"><linktext>Interrupt

Handling</linktext></link>

<link href="GUID-E55F9286-F586-4665-93D8-86F1E7BE2C7C.dita"><linktext>SMP Developer

Tips</linktext></link>

</related-links></concept>