kernel/eka/memmodel/epoc/direct/minit.cpp
author Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
Sat, 20 Feb 2010 00:10:51 +0200
branchRCL_3
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child 43 c1f20ce4abcf
permissions -rw-r--r--
Revision: 201007 Kit: 201007
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// Copyright (c) 1996-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\memmodel\epoc\direct\minit.cpp
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// 
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//
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#include <memmodel.h>
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#include "cache_maintenance.h"
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_LIT(KLitRamAlloc,"RamAlloc");
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const TInt KMaxSupervisorStackSpace=0x200000;
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void M::Init1()
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	{
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	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("M::Init1"));
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	MM::UserDataSectionBase=TheRomHeader().iUserDataAddress;
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	MM::UserRomDataSectionEnd=TheRomHeader().iUserDataAddress+TheRomHeader().iTotalUserDataSize;
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	MM::UserDataSectionEnd = TheSuperPage().iRamBase + TheSuperPage().iTotalRamSize;
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	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("MM::UserDataSectionBase=%08x",MM::UserDataSectionBase));
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	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("MM::UserRomDataSectionEnd=%08x",MM::UserRomDataSectionEnd));
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	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("MM::UserDataSectionEnd=%08x",MM::UserDataSectionEnd));
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	// Memory model dependent CPU stuff
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	MM::Init1();
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	// Set up cache info
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	CacheMaintenance::Init1();
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	}
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void M::Init2()
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	{
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	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("M::Init2"));
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	TInt userRam=MM::UserDataSectionEnd-MM::UserDataSectionBase;
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	TInt blocks=userRam>>MM::RamBlockShift;
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	MM::RamAllocator=TBitMapAllocator::New(blocks,ETrue);
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	if (!MM::RamAllocator)
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		MM::Panic(MM::ERamAllocCreateFailed);
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	TInt used_blocks=(MM::UserRomDataSectionEnd-MM::UserDataSectionBase)>>MM::RamBlockShift;
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	if (used_blocks)
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		MM::RamAllocator->Alloc(0,used_blocks);
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	__KTRACE_OPT(KBOOT,Kern::Printf("%d blocks, %d used",blocks,used_blocks));
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	TInt r=K::MutexCreate((DMutex*&)MM::RamAllocatorMutex, KLitRamAlloc, NULL, EFalse, KMutexOrdRamAlloc);
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	if (r!=KErrNone)
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		MM::Panic(MM::ERamAllocMutexCreateFailed);
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	const SRamBank* banks = (const SRamBank*)TheSuperPage().iRamBootData;
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	TInt nBanks = 0;
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	TInt maxBankBlocks = 0;
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	TInt bnum = 0;
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	const SRamBank* pB = banks;
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	for (; pB->iSize; ++nBanks, ++pB)
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		{
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		TInt nblocks = pB->iSize >> MM::RamBlockShift;
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		TInt abnum = bnum &~ 31;
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		TInt a_end = (bnum + nblocks + 31)&~31;
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		TInt a_count = a_end - abnum;
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		if (a_count > maxBankBlocks)
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			maxBankBlocks = a_count;
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		bnum += (pB->iSize >> MM::RamBlockShift);
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		}
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	__KTRACE_OPT(KBOOT,Kern::Printf("%d banks, max bank blocks %08x", nBanks, maxBankBlocks));
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	if (nBanks>1)
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		{
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		MM::SecondaryAllocator = TBitMapAllocator::New(maxBankBlocks, ETrue);
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		if (!MM::SecondaryAllocator)
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			MM::Panic(MM::ESecAllocCreateFailed);
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		}
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	}
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void M::Init3()
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	{
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	// Third phase MMU initialisation
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	}
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void M::Init4()
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    {
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    // Fourth phase MMU initialisation - Not required on this memory model.
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    }
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0
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TInt M::InitSvHeapChunk(DChunk* aChunk, TInt aSize)
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	{
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	DMemModelChunk* pC=(DMemModelChunk*)aChunk;
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	TLinAddr base = TheRomHeader().iKernDataAddress;
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	K::HeapInfo.iChunk = aChunk;
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	K::HeapInfo.iBase = (TUint8*)base;
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	K::HeapInfo.iMaxSize = pC->MaxSize();
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	pC->SetFixedAddress(base, aSize);
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	__KTRACE_OPT(KBOOT,Kern::Printf("Created SvHeap chunk, addr %08X, init size %08X max size %08X",pC->Base(),aSize,pC->MaxSize()));
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	return KErrNone;
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	}
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TInt M::InitSvStackChunk()
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	{
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	return KErrNone;
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	}
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